Noisy Gradient Descent Bit-Flip Decoding for LDPC Codes

A modified Gradient Descent Bit Flipping (GDBF) algorithm is proposed for decoding Low Density Parity Check (LDPC) codes on the binary-input additive white Gaussian noise channel. The new algorithm, called Noisy GDBF (NGDBF), introduces a random perturbation into each symbol metric at each iteration. The noise perturbation allows the algorithm to escape from undesirable local maxima, resulting in improved performance. A combination of heuristic improvements to the algorithm are proposed and evaluated. When the proposed heuristics are applied, NGDBF performs better than any previously reported GDBF variant, and comes within 0.5 dB of the belief propagation algorithm for several tested codes. Unlike other previous GDBF algorithms that provide an escape from local maxima, the proposed algorithm uses only local, fully parallelizable operations and does not require computing a global objective function or a sort over symbol metrics, making it highly efficient in comparison. The proposed NGDBF algorithm requires channel state information which must be obtained from a signal to noise ratio (SNR) estimator. Architectural details are presented for implementing the NGDBF algorithm. Complexity analysis and optimizations are also discussed.Comment: 16 pages, 22 figures, 2 table

CMOS analog map decoder for (8,4) hamming code

Journal ArticleAbstract-Design and test results for a fully integrated translinear tail-biting MAP error-control decoder are presented. Decoder designs have been reported for various applications which make use of analog computation, mostly for Viterbi-style decoders. MAP decoders are more complex, and are necessary components of powerful iterative decoding systems such as Turbo codes. Analog circuits may require less area and power than digital implementations in high-speed iterative applications. Our (8, 4) Hamming decoder, implemented in an AMI 0.5- m process, is the first functioning CMOS analog MAP decoder. While designed to operate in subthreshold, the decoder also functions above threshold with a small performance penalty. The chip has been tested at bit rates up to 2 Mb/s, and simulations indicate a top speed of about 10 Mb/s in strong inversion. The decoder circuit size is 0.82 mm2, and typical power consumption is 1 mW at 1 Mb/s

Analog decoding of product codes

Journal ArticleAbstract - A method is presented for analog softdecision decoding of block product codes (block turbo codes). Extrinsic information is exchanged as analog signals between component row and column decoders. The component MAP decoders use low-power analog computation in subthreshold CMOS circuits to implement the sum-product algorithm. An example decoder design is presented for a (16,ll)? Hamming code

Analog MAP decoder for (8, 4) hamming code in subthreshold CMOS

Journal ArticleAbstract - An all-MOS analog tail-biting MAP decoder is presented for an (8,4) Hamming code. The decoder implements a probability propagation algorithm using subthreshold CMOS networks. Physical results verify the expected behavior of the decoderand demonstrate robustness of analog decoding circuits

Analog MAP decoder for (8, 4) hamming code in subthreshold CMOS

Journal ArticleAn all-MOS analog implementation of a MAP decoder is presented for the (8, 4) extended Hamming code. This paper describes the design and analysis of a tail-biting trellis decoder implementation using subthreshold CMOS devices. A VLSI test chip has recently returned from fabrication, and preliminary test results indicate accurate decoding up to 20 MBit/s

Analog decoding of product codes

Journal ArticleA design approach is presented for soft-decision decoding of block product codes ("block turbo codes") using analog computation with MOS devices. Application of analog decoding to large code sizes is also considered with the introduction of serial analog interfaces and pipeline schedules

Cybersecurity of Autonomous Vehicle Platooning

Human mistakes are the main source of fatal accidents and daily traffic congestion. Recent researches have focused on assisting drivers to mitigate traffic fatalities and create more enjoyable drive experiences. Vehicle platooning or cooperative adaptive cruise control (CACC) has been stated as one of the most effective solutions to tackle this problem. Platooning concept involves a group of vehicles act as a single unit through coordination of movements. This concept draws a special attention among academia and governmental and non-governmental organizations. Recently, there have been several demonstrations, which have introduced the potential benefits of this idea, e.g. safety enhancement, increase roadway capacity, and improve traffic efficiency. While many aspects of platooning such as transportation impacts, mechanical and control concerns are still under investigation, very limited amount of work has studied platooning in an adversarial environment. To design safe distributed controllers and networks, it is essential to understand the possible attacks that can be applied against platoons. In this work, we design a set of insider attack and abnormal behaviors that are implemented in a car platoon. For example, an attack has been introduced, in which attacker exploits the platoon controller to cause collisions and disrupt the performance of platoon. In the small platoon, this successful attack can be carried through a malicious member of platoon solely by changing its motion (acceleration and deceleration) and gains of the controller. However, the attack should be executed through a collaborative effort in large platoons. In this case, the main attacker not only adjusts its gains and motion to accomplish the attack but also collaborates with the other attacker. Another attacker only uses the gain modification technique. The strong point of the proposed attack is that attacker stays intact while in existing works from literature, the attacker gets affected during an attack

Analog MAP decoder for (8,4) hamming code in subthreshold CMOS

Journal ArticleAn all-MOS analog tail-biting MAP decoder is presented for an (8,4) Hamming code. The decoder implements a probability propagation algorithm using subthreshold CMOS networks. Physical results verify the expected behavior of the decoder and demonstrate robustness of analog decoding circuits

Reducing the impact of internal upsets inside the correlation process in GPS Receivers

International audience—This paper 1 examines two approaches to deal with internal logic upsets inside correlation process used in the tracking process of GPS receivers. These upsets can be produced due to process/voltage and temperature variations coupled with increased advancement of CMOS technology. If any upset occurs when computing the correlation function during each 10 ms, then errors are propagated in tracking loops, resulting in a loss of the GPS signal tracking and a distorted position given by the receiver. Results of experiments using a GPS receiver design are presented in this paper to evaluate the performance of each method. The two proposed solutions (the Feedback freezing loop (FFL) and the Last Correct Value (LCV) methods) offer a big interest compared to the classical Triple Modular Redundancy (TMR) method since they provide the same performance as the TMR with low area complexity. This work can be extended to any system using feedback loops information